Forum Discussion
NShan12
Occasional Contributor
Occasional ContributorTiming analysis error on Asynchronous control signals
Hello,
In my design, there is an asynchronous bus between FPGA and Microcontroller (Master). FPGA uses the edges on the signals WRN (Write active) and ALE (Address Enable) to classify if the signa...
sstrell
Super Contributor
Super ContributorIf your code from 11/2/21 is still the same, you are still coding these signals like clocked processes instead of combinatorial logic. You should look at adjusting your code such that the signals no longer look like clock signals to the compiler.
