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NShan12's avatar
NShan12
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Timing analysis error on Asynchronous control signals

Hello, In my design, there is an asynchronous bus between FPGA and Microcontroller (Master). FPGA uses the edges on the signals WRN (Write active) and ALE (Address Enable) to classify if the signa...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

If your code from 11/2/21 is still the same, you are still coding these signals like clocked processes instead of combinatorial logic. You should look at adjusting your code such that the signals no longer look like clock signals to the compiler.