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NShan12's avatar
NShan12
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Timing analysis error on Asynchronous control signals

Hello, In my design, there is an asynchronous bus between FPGA and Microcontroller (Master). FPGA uses the edges on the signals WRN (Write active) and ALE (Address Enable) to classify if the signa...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi Naveen,


Can you click on check timing report and see if there is no clock report. You can see details of the no clock ignored as the warning mentioned that. You can see the target node of the clock with reason.




NShan12's avatar
NShan12
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hello @SyafieqS ,

Sorry for a late reply. I could not check with 21.1 STD.

But with QP20.1.1 STD, I find these results:

1. The two unconstrained clocks are ALE and WRN.

2. The check timing report: I guess the number 75 indicates the total number of cells which are controlled by ALE and WRN .