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NShan12
Occasional Contributor
Occasional ContributorTiming analysis error on Asynchronous control signals
Hello,
In my design, there is an asynchronous bus between FPGA and Microcontroller (Master). FPGA uses the edges on the signals WRN (Write active) and ALE (Address Enable) to classify if the signa...
SyafieqS
Super Contributor
Super ContributorHi Naveen,
Speaking of legacy, you must be using the snippet to previous Quartus. What Quartus you are using now and prior to this? Can you try to use latest release and see if there is clock warning?
NShan12Occasional Contributor
Occasional ContributorHi SyafieqS_Intel,
I am using Quartus 20.1.1 Standard. All the information/code and screenshots I have shared are from the same version.
The legacy design was developed in MAXPLUS II.
Thank you.
