Forum Discussion
NShan12
Occasional Contributor
Occasional ContributorTiming analysis error on Asynchronous control signals
Hello,
In my design, there is an asynchronous bus between FPGA and Microcontroller (Master). FPGA uses the edges on the signals WRN (Write active) and ALE (Address Enable) to classify if the signa...
SyafieqS
Super Contributor
Super ContributorNaveen,
If thats the case, my suggestion is to check Ignored Constrain Report in Timing Analyzer. I suspect that few clock constraint has been neglected for some reason. Once you identified it, make sure the clock is valid, you can use node finder and check the node if it exist.
NShan12Occasional Contributor
Occasional ContributorHello,
I checked the ignored constraints report in Timing analyser. It shows no constraints are ignored. See screenshot below:
But the warning: "Warning (332060): Node: WRN was determined to be a clock but was found without an associated clock assignment." still remains. Just to remind you, I am not using edges of WRN to latch data. I do not understand why WRN is considered as a clock even though I am not coding it as a clock.
Thank you!
