Forum Discussion
NShan12
Occasional Contributor
Occasional ContributorTiming analysis error on Asynchronous control signals
Hello,
In my design, there is an asynchronous bus between FPGA and Microcontroller (Master). FPGA uses the edges on the signals WRN (Write active) and ALE (Address Enable) to classify if the signa...
SyafieqS
Super Contributor
Super ContributorHi Naveen,
Let me know if there is any update from previous reply?
Are you able to constrain the clocks?
NShan12Occasional Contributor
Occasional ContributorHello @SyafieqS , sorry for a delayed reply. Held up with too many topics.
To replace false path to clock groups, I should first create clock constraints on WRN and ALE. This is as per Intel's example set clock groups constraint:
But since ALE and WRN are just address latch and write enable signals they do not have a clock period. So, I do not know how to write a generate clock constraint on ALE and WRN.
The below screenshot shows the behaviour of ALE and WRN during a bus write cycle:
Thank you.
