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NShan12's avatar
NShan12
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4 years ago

Timing analysis error on Asynchronous control signals

Hello, In my design, there is an asynchronous bus between FPGA and Microcontroller (Master). FPGA uses the edges on the signals WRN (Write active) and ALE (Address Enable) to classify if the signa...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi Naveen,


Let me know if there is any update from previous reply?

Are you able to constrain the clocks?


NShan12's avatar
NShan12
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hello @SyafieqS , sorry for a delayed reply. Held up with too many topics.

To replace false path to clock groups, I should first create clock constraints on WRN and ALE. This is as per Intel's example set clock groups constraint:

But since ALE and WRN are just address latch and write enable signals they do not have a clock period. So, I do not know how to write a generate clock constraint on ALE and WRN.

The below screenshot shows the behaviour of ALE and WRN during a bus write cycle:

Thank you.