system design using cyclone II

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Thanks dave, the web described blockgram works in a similar way as I described except that I am using the ALT_PLL to build my phase locked loop. but still. how can I compromise the difference between 154Khz and the lowest required ALT_PLL frequency 10MHz?

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You do not need a PLL operating at 154kHz. You need a complex-valued sinusoid operating at 154kHz. You get that using an ALT_PLL operating at 10MHz or more plus a Numerically Controller Oscillator (NCO) as provided by Altera;

http://www.altera.com/literature/ug/ug_nco.pdf

Re-read the SRS data sheet. They describe how their sinusoid is 24-bits. This means they have an NCO with 24-bits of output amplitude precision. I think the DSP blocks within the Cyclone II FPGAs can implement 9x9-bit, and 18x18-bit multiplications, so 18-bits of NCO precision would be easily handled. You need to work out your signal-to-noise requirements to determine how many bits you need in your design.

Cheers,

Dave

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The current is obtained from a position detection sensor(PSD) which transfers light into current in order to calculate the position where the light is located on the sensor.

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This is still not clear. You do not indicate why the light would change at 154kHz. Is the light being 'chopped'. Could you please post a diagram of your setup?

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The lock-in amplifier consists of a PLL, a mixer and a LPF. The PLL is to generate a reference signal which also is 154Khz. The locked signal and the referenced signal will be sent to the mixer and the LPF will keep the DC component of the output, which is proportional to the amplitude of the original signal of interested.

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Right. In an FPGA, there would be a PLL, but at a much higher frequency that 154kHz. Inside the FPGA, the PLL would be used to clock a Numerically Controller Oscillator, and the output of that oscillator is a digital sinusoid and cosinusoid. One of those signals can be sent to a digital-to-analog converter (DAC) and filtered to give you a very clean 154kHz reference signal. That signal can be used to drive the sensors in your system.

The sensor output would then be sampled by an analog-to-digital coverter (ADC). The samples would then internally be multiplied by the digital versions of the NCO outputs, i.e., your samples x(t) would be demodulated by the compex-exponential exp(-j*2*pi*fo*t) = cos(2*pi*fo*t) - j*sin(2*pi*f0*t), where f0 = 154kHz, and t = n/fs, where n is the sample index and fs is the sampling frequency. The complex-valued baseband signal would then pass through two digital filters.

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About the ADC, at first I was thinking of using the Virtex 6 with AD/DA, that's where I got the information. like I said I was new to hardware design so I really don't know much about the AD/DA selection...thanks for the information.

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You're on the wrong group if you want help with Xilinx FPGAs. However, the above description would work fine with those parts too.

For more details on FPGA signal processing read these documents:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf)

Cheers,

Dave

Read the last page of this:

http://www.thinksrs.com/downloads/pdfs/catalog/sr850c.pdf

The FPGA can implement this same logic.

As I comment above, if the FPGA can also be the source of the sinusoid source, then the system design becomes a lot simpler.

Cheers,

Dave

Thx for the reply. I will try to make it clearer since I am new to hardware design...

The current is obtained from a position detection sensor(PSD) which transfers light into current in order to calculate the position where the light is located on the sensor. After analog processing(which is completed by another colleague), our interested signal frequency is 154Khz. Usually there are signals from other frequency bands so the noise is extremely large. That's why I wanna use a lock-in amplifier.

The lock-in amplifier consists of a PLL, a mixer and a LPF. The PLL is to generate a reference signal which also is 154Khz. The locked signal and the referenced signal will be sent to the mixer and the LPF will keep the DC component of the output, which is proportional to the amplitude of the original signal of interested.

The lock-in amplifier will be implemented in FPGA. There will be other DSP processing in FPGA using DSP kit, but I'm not there yet.:p

About the ADC, at first I was thinking of using the Virtex 6 with AD/DA, that's where I got the information. like I said I was new to hardware design so I really don't know much about the AD/DA selection...thanks for the information.

Are you trying to build this?

http://en.wikipedia.org/wiki/lock-in_amplifier

What is the carrier of the signal? 154kHz?

What you need inside the FPGA is a Numerically Controller Oscillator to act as your reference sinusoid, a mixer (multiplication), and a low-pass filter. The output from the filter can be a complex-valued baseband signal from which you can obtain magnitude and phase information.

Can you control the frequency of the sinusoid you are trying to detect? Is it phase-locked to a common reference?

If so, you can phase-lock the FPGA to the same reference, generate the identical sinusoid frequency, and your digital filter output will measure the amplitude and phase of the external sinusoid.

If you do not know the frequency exactly, then you can design the NCO to have a programmable frequency and you can sweep the frequency until you find the peak at the filter output. You can also reproduce the circuit several times, measuring the response at several closely spaced frequencies. You can peak-up the system to have the center channel with the maximum value. If the sinusoid drifts, you will see the amplitude in the other channels get too large, and you can adjust the NCO frequencies appropriately.

There would be other solutions possible using FFTs and the Goertzel algorithm too (they can be implemented using IIR filters).

http://en.wikipedia.org/wiki/goertzel_algorithm

I'm sure you are not the first person to attempt to build a digital version of this lock-in amplifier. Now that you know the relevant digital terminology, you can research what people have had success with.

Cheers,

Dave

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I am trying to implement a hardware system which uses current to compute distances. The incoming current is obtained from a sensor, and will be sampled and input into my FPGA. The ADC is 14bit, 250MSPS. A lock-in amplifier will be designed within the FPGA to extract the noise from a large amount of noise.

Now my problem is: My current signal is 154KHz. When I tried to build a PLL module using the ALT_PLL megafunction, the lowest required input frequency is 10MHz...

Now I am thinking of using two PLL modules, one to divide the 10MHz into 154Khz, if that is possible, the other to create its reference signal. Am I doing the right way? Is there a better way?

Also, I guess I need to build a buffer before ADC. but I dont know what type of buffer / where to get information about that. Could anyone help me?

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What are the signal processing steps that the 'lock-in amplifier' is supposed to do? It sounds to me like you are trying to implement an analog solution (using the FPGA PLL), where a digital solution might be possible.

Why use a 250MHz ADC if your signal of interest is located at 154kHz? The analog front-end (ADC buffer) needs to be designed to pass the signal frequencies of interest, while suppressing noise outside the band you are interested in. So what are those frequencies? Does your ADC need to be 14-bits? The number of bits impacts the signal processing path data width.

If you can provide a clearer description on what you are trying to achieve is the general context of signal processing, I am sure you will get some feedback from this forum.

Cheers,

Dave