system design using cyclone II

--- Quote Start ---

The current is obtained from a position detection sensor(PSD) which transfers light into current in order to calculate the position where the light is located on the sensor.

--- Quote End ---

This is still not clear. You do not indicate why the light would change at 154kHz. Is the light being 'chopped'. Could you please post a diagram of your setup?

--- Quote Start ---

The lock-in amplifier consists of a PLL, a mixer and a LPF. The PLL is to generate a reference signal which also is 154Khz. The locked signal and the referenced signal will be sent to the mixer and the LPF will keep the DC component of the output, which is proportional to the amplitude of the original signal of interested.

--- Quote End ---

Right. In an FPGA, there would be a PLL, but at a much higher frequency that 154kHz. Inside the FPGA, the PLL would be used to clock a Numerically Controller Oscillator, and the output of that oscillator is a digital sinusoid and cosinusoid. One of those signals can be sent to a digital-to-analog converter (DAC) and filtered to give you a very clean 154kHz reference signal. That signal can be used to drive the sensors in your system.

The sensor output would then be sampled by an analog-to-digital coverter (ADC). The samples would then internally be multiplied by the digital versions of the NCO outputs, i.e., your samples x(t) would be demodulated by the compex-exponential exp(-j*2*pi*fo*t) = cos(2*pi*fo*t) - j*sin(2*pi*f0*t), where f0 = 154kHz, and t = n/fs, where n is the sample index and fs is the sampling frequency. The complex-valued baseband signal would then pass through two digital filters.

--- Quote Start ---

About the ADC, at first I was thinking of using the Virtex 6 with AD/DA, that's where I got the information. like I said I was new to hardware design so I really don't know much about the AD/DA selection...thanks for the information.

--- Quote End ---

You're on the wrong group if you want help with Xilinx FPGAs. However, the above description would work fine with those parts too.

For more details on FPGA signal processing read these documents:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf)

Cheers,

Dave