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Altera_Forum
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14 years ago

system design using cyclone II

Hi, I am trying to implement a hardware system which uses current to compute distances. The incoming current is obtained from a sensor, and will be sampled and input into my FPGA. The ADC is 14...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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Thanks dave, the web described blockgram works in a similar way as I described except that I am using the ALT_PLL to build my phase locked loop. but still. how can I compromise the difference between 154Khz and the lowest required ALT_PLL frequency 10MHz?

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You do not need a PLL operating at 154kHz. You need a complex-valued sinusoid operating at 154kHz. You get that using an ALT_PLL operating at 10MHz or more plus a Numerically Controller Oscillator (NCO) as provided by Altera;

http://www.altera.com/literature/ug/ug_nco.pdf

Re-read the SRS data sheet. They describe how their sinusoid is 24-bits. This means they have an NCO with 24-bits of output amplitude precision. I think the DSP blocks within the Cyclone II FPGAs can implement 9x9-bit, and 18x18-bit multiplications, so 18-bits of NCO precision would be easily handled. You need to work out your signal-to-noise requirements to determine how many bits you need in your design.

Cheers,

Dave