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I am trying to implement a hardware system which uses current to compute distances. The incoming current is obtained from a sensor, and will be sampled and input into my FPGA. The ADC is 14bit, 250MSPS. A lock-in amplifier will be designed within the FPGA to extract the noise from a large amount of noise.
Now my problem is: My current signal is 154KHz. When I tried to build a PLL module using the ALT_PLL megafunction, the lowest required input frequency is 10MHz...
Now I am thinking of using two PLL modules, one to divide the 10MHz into 154Khz, if that is possible, the other to create its reference signal. Am I doing the right way? Is there a better way?
Also, I guess I need to build a buffer before ADC. but I dont know what type of buffer / where to get information about that. Could anyone help me?
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What are the signal processing steps that the 'lock-in amplifier' is supposed to do? It sounds to me like you are trying to implement an analog solution (using the FPGA PLL), where a digital solution might be possible.
Why use a 250MHz ADC if your signal of interest is located at 154kHz? The analog front-end (ADC buffer) needs to be designed to pass the signal frequencies of interest, while suppressing noise outside the band you are interested in. So what are those frequencies? Does your ADC need to be 14-bits? The number of bits impacts the signal processing path data width.
If you can provide a clearer description on what you are trying to achieve is the general context of signal processing, I am sure you will get some feedback from this forum.
Cheers,
Dave
Honored Contributor
