system design using cyclone II

Are you trying to build this?

http://en.wikipedia.org/wiki/lock-in_amplifier

What is the carrier of the signal? 154kHz?

What you need inside the FPGA is a Numerically Controller Oscillator to act as your reference sinusoid, a mixer (multiplication), and a low-pass filter. The output from the filter can be a complex-valued baseband signal from which you can obtain magnitude and phase information.

Can you control the frequency of the sinusoid you are trying to detect? Is it phase-locked to a common reference?

If so, you can phase-lock the FPGA to the same reference, generate the identical sinusoid frequency, and your digital filter output will measure the amplitude and phase of the external sinusoid.

If you do not know the frequency exactly, then you can design the NCO to have a programmable frequency and you can sweep the frequency until you find the peak at the filter output. You can also reproduce the circuit several times, measuring the response at several closely spaced frequencies. You can peak-up the system to have the center channel with the maximum value. If the sinusoid drifts, you will see the amplitude in the other channels get too large, and you can adjust the NCO frequencies appropriately.

There would be other solutions possible using FFTs and the Goertzel algorithm too (they can be implemented using IIR filters).

http://en.wikipedia.org/wiki/goertzel_algorithm

I'm sure you are not the first person to attempt to build a digital version of this lock-in amplifier. Now that you know the relevant digital terminology, you can research what people have had success with.

Cheers,

Dave