New ContributorStratix 10 PHYLite avalon bus avl_readdata seems to be synthesized away
Hi Altera AE ,
We are working on a design on Stratix 10 using PHYLite library.
We previously use Arria 10 PHYLite in our last project, it was smooth and we didn't encounter any problem in Arria 10.
In Stratix 10, the waitrequest signal was stuck at high all the time
before we issue any command to the avalon bus after reset.
We solved this by issuing a number of dummy write commands to avalon bus, the waitrequest signal returns to 0.
We got help from Altera AE on this issue, and now we see another issue thus I raise a post here.
After solving the waitrequest issue, we continue to read the basic information from the avalon bus,
we can see the readdata_valid pulse in signal tap but avl_readdata is always 0
when we read the address 0x05000024.
We don't see anything wrong in the RTL, but we see that the avl_readdata is always 0.
Until we make an irrelevant change to the code, the avl_readdata becomes normal again such that the readdata_valid looks the same as what it is when the avl_readdata is 0.
It is so weird, we spent a couple of days on this.
Please help us on this, we have been stuck on the avalon bus communication for 3 months.
FYI : we are using quartus version 19.3
Thanks,
Samson
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