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LHinC1's avatar
LHinC1
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5 years ago

Stratix 10 PHYLite avalon bus avl_readdata seems to be synthesized away

Hi Altera AE , We are working on a design on Stratix 10 using PHYLite library. We previously use Arria 10 PHYLite in our last project, it was smooth and we didn't encounter any pr...
Rashmi1's avatar
Rashmi1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi Samson,


It seems like the write transaction isn’t completing prior to the read transaction.

How are you verifying if transfer of all the write data for the write transaction?


Thanks,

Rashmi


  • LHinC1's avatar
    LHinC1
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hello Rashmi,

    We are accessing the PhyLite through the Avalon bus,

    We read the indirect address from the address 0x05000024.

    It does not require any write command before reading data, is it correct?

    I attach the table copied from Phy Lite user guide.

    We did the same thing in our last Arria 10 design.

    I encounter this problem when I move our design to Stratix 10 device.

    Thanks,

    Samson