About writing JBC files using altera-stapl

We are currently attempting to update the FPGA on a MAX 10 (10M16SCU169I7G) from the SoM using a JBC file written via altera-stapl, which is based on jamplayer. However, the programming process is failing.

From the log, the following messages appear at the end, and it seems that the process terminates as an unrecognized device after the “No SLD node” detection:

No SLD node

Unrecognized device

Exit code = 6... Unrecognized device

Program took 15.000000 seconds to execute.

We are using Quartus Prime Lite 25.1 to create the JBC file.

The JBC file is created by converting a POF file generated by Quartus into a JAM file using Quartus Programmer, then adding one line of source code to the JAM file, and finally converting it into JBC using quartus_jbcc.exe.

Could this mean that there is something wrong with the way the JBC file is generated?

When we create a JBC file from an SOF file using the same procedure, programming succeeds, so we believe there may not be an issue with the JBC file generation method itself.

Since altera-stapl is relatively old, could there be compatibility issues with Quartus as well?
If so, which Quartus version or earlier should we use?