Forum Discussion

LHinC1's avatar
LHinC1
Icon for New Contributor rankNew Contributor
5 years ago

Stratix 10 PHYLite avalon bus avl_readdata seems to be synthesized away

Hi Altera AE , We are working on a design on Stratix 10 using PHYLite library. We previously use Arria 10 PHYLite in our last project, it was smooth and we didn't encounter any pr...
Rashmi1's avatar
Rashmi1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi Samson,


Do you mind to share what’s the irrelevant code change to fix the avl_data 0?

For this avl_data is 0, I would think we can check the pin assigned by checking the correct lane or pin addresses that are assigned correctly. You can refer to this PHYlite wiki page to get the correct addresses.


Thanks,

Rashmi


LHinC1's avatar
LHinC1
Icon for New Contributor rankNew Contributor
5 years ago

Hello Rashmi,

We just changed a single line in our design, then we get the following result.

I attached a picture "SignalTap.png".

We just changed one single line in a state machine that interfaces with the avalon bus.

The difference is shown in "before (failed).png" and "after (working).png".

I also attached my code "TC4200ST_L_19_3_20200728.qar", this one is the working one.

Thanks,

Samson