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LHinC1's avatar
LHinC1
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5 years ago

Stratix 10 PHYLite avalon bus avl_readdata seems to be synthesized away

Hi Altera AE , We are working on a design on Stratix 10 using PHYLite library. We previously use Arria 10 PHYLite in our last project, it was smooth and we didn't encounter any pr...
Rashmi1's avatar
Rashmi1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

I do find this INI below in the design, can I know what’s the use of the INI? I would think this INI will no impact on this issue, just for understanding.

bypass_vid_when_pmbus_mode_master_all_slave_address_3f = on i8XOhQg3u5 = 9WdkQrX0sx

Also, the customer can run the design in the A10 board while migrating the design to S10, they faced this issue.

Can I know which the Avalon fie that the you modified? Please point me there. Thanks.


LHinC1's avatar
LHinC1
Icon for New Contributor rankNew Contributor
5 years ago

Hello Rashmi,

I think the ini file was created by Quartus Prime software. We encountered an issue at the beginning regarding the Stratix 10 Smart VID. We got an answer in the forum and then we followed the solution provided in Altera forum.

We did not copy the PHY Lite library code from our Arria 10 design, as we saw there are lots of differences between the PHY Lite files generated in Quartus 16.0 for our Arria 10 design and the PHY Lite files generated in the Quartus Prime 19.3. So we regenerated all the necessary files in Quartus Prime 19.3 for our Stratix 10 project.

By the way, did you reproduce the same situation as we saw?

Thanks,

Samson