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LHinC1's avatar
LHinC1
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6 years ago

Stratix 10 PHYLite avalon bus avl_readdata seems to be synthesized away

Hi Altera AE , We are working on a design on Stratix 10 using PHYLite library. We previously use Arria 10 PHYLite in our last project, it was smooth and we didn't encounter any pr...
IntelSupport's avatar
IntelSupport
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6 years ago

Hi Samson,


Thank you for reaching out to Intel Forum. My name is Rashmi.


can you please provide me with project to reproduce the issue at my end also the screen shots of signal taps of the signals .


Regards,

Rashmi


LHinC1's avatar
LHinC1
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6 years ago

Hello Rashmi,

Thank you for your support.

I have attached my code and the screenshots.

Thanks,

Samson