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Altera_Forum
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18 years ago

Strange effect with Stratix FPGA

Hello!

I am using a Stratix EP1S10 device on a NIOS II Development Board. I use it for VHDL programming only. That means, I don't use any NIOS stuff in my project. I made my own user configuration with which I configure the FPGA. Up to now, all works fine.

Now, I have implemented a shift register in my project which works fine, too. It is 850 shifts deep and shifts a 11 bit wide vector. Parallel to the shift register I implemented some logic, which examines the contents of certain shift register parts. That works fine, too, up to the moment, when the parallel logic becomes maybe too complex. Then there are strange effects on my board I can`t explain myself.

For example there is a dot in the seven segment displays on my board wich is connected to the pin D19 of the FPGA, which gets active, although I never assigned the PIN D19 in the pin assignment editor. Another effect is, that the output of the FPGA is no more compatible with the output of the simulator in Quatus II, where all works as expected.

When I remove some logic off the shift register, it is all right again.

I know, it is hard for you to answer that, when you don't know my project, but it could be, that somone of you had similar experience (especially with the dot, which is active although it is not assigned or somethink like that), and can give me some hints, why this happens.

Greets

Maik

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  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I think, that all IOs I use are assigned right, and there should be no conflicts with other board components, because I use the so called prototyping connectors of the board for the ADC connection. The UART interface and the seven-segment display, too, do not share their resources with other componets.

    Hmm, it sounds like a lot of additional work, if I have to assign every pin which is connected to an external component. The board is very complex, with SRAM, SDRAM, Eth Phy, 2 UARTS. That would be a lot of logic, I have to spend on these pins.

    Is there no way, to turn unused pins completly off?
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Since you are asking me for specifics.

    I would set the tool for Un-used pins as inputs with Tri-state pull up.

    I would look at each IC that is attached to the FPGA.

    If it has the ability to present noise on the inputs, I would see what Output pin will place that chip in turned off mode (none chip select).

    I would then drive that output pin to the appropriate high or low level to achieve that goal.

    Passive input pins from passive external logic will be covered by the above un-used pins settings.

    That is what you should do in my 30 years of experence (humble opinion).

    I hope this helps.

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  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    --- Quote Start ---

    I would set the tool for Un-used pins as inputs with Tri-state pull up.

    --- Quote End ---

    I allready did this, but this

    --- Quote Start ---

    I would see what Output pin will place that chip in turned off mode (none chip select).

    --- Quote End ---

    is a great idea. I will try this tomorrow, and see if it will work!

    Thanks!

    Maik
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Remove the clock (x-tal) and you can see the difference between dynamic + static and static power consumption. Make sure the clock is realy gone by gnd-ing the input otherwise it may pickup noise instead. Datasheets tells you the static power consumption. Maybe that can give you a hint.

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi larsen!

    Thanks for your participation to this thread!

    I think I identified the evildoer. It seems to be the LAN91C111 on my board. When I run my own configuration, he becomes hot as hell. When I reload the NIOS configuration with which the board was delivered (and which I use every time, I reconfigure the FPGA with my configuration), the LAN91C111 becomes hot, too, but not quite as hot, as with my configuration (I wonder how he even survived this all the time . . . )

    Now, I have a problem: I looked for a pin on the LAN91C111 that says "turn me off" or something like that. But there isn't one. Instead I have to write some bits into some configuration registers I would like to be able to access, but I do not understand the datasheet of this fellow, at all (http://www.smsc.com/main/datasheets/91c111.pdf (http://www.smsc.com/main/datasheets/91c111.pdf)).

    Is there anybody out there, who can give me some advise, how to write a simple disable entity for this chip?

    Greets,

    Maik
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Why don' t You import the Pin Assigment from a sample design for the development board You are using and modify only the Pin assignments specific to Your design. I have been working with a CYCLONE Development Board sample designs which also shows how to place the LAN Controller in a quiescent state.

    When using development board to host my custom design, I found always usesful to open an existing sample design delete their logic and implement my logic; this clears all the board interfacing issues (inlcuding FPGA configuration issues) and allows me to focus on the actual design that I am trying to prototype.