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Altera_Forum
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18 years ago

Strange effect with Stratix FPGA

Hello! I am using a Stratix EP1S10 device on a NIOS II Development Board. I use it for VHDL programming only. That means, I don't use any NIOS stuff in my project. I made my own user configurat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I think, that all IOs I use are assigned right, and there should be no conflicts with other board components, because I use the so called prototyping connectors of the board for the ADC connection. The UART interface and the seven-segment display, too, do not share their resources with other componets.

Hmm, it sounds like a lot of additional work, if I have to assign every pin which is connected to an external component. The board is very complex, with SRAM, SDRAM, Eth Phy, 2 UARTS. That would be a lot of logic, I have to spend on these pins.

Is there no way, to turn unused pins completly off?