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Altera_Forum
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18 years ago

Strange effect with Stratix FPGA

Hello! I am using a Stratix EP1S10 device on a NIOS II Development Board. I use it for VHDL programming only. That means, I don't use any NIOS stuff in my project. I made my own user configurat...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Remove the clock (x-tal) and you can see the difference between dynamic + static and static power consumption. Make sure the clock is realy gone by gnd-ing the input otherwise it may pickup noise instead. Datasheets tells you the static power consumption. Maybe that can give you a hint.