Strange effect with Stratix FPGA

Since you are asking me for specifics.

I would set the tool for Un-used pins as inputs with Tri-state pull up.

I would look at each IC that is attached to the FPGA.

If it has the ability to present noise on the inputs, I would see what Output pin will place that chip in turned off mode (none chip select).

I would then drive that output pin to the appropriate high or low level to achieve that goal.

Passive input pins from passive external logic will be covered by the above un-used pins settings.

That is what you should do in my 30 years of experence (humble opinion).

I hope this helps.

Avatar