SSN and reserve pins as ground

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I know that we ran into some problems with the PCI (in the Virtex-5 FPGA) when connected to some specific backplane PCB, it is possible that this was an SSN problem.

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What type of backplane? CompactPCI or regular PCI?

Cheers,

Dave

Yeah, I'll have to think about it. In all of our previous designs, we connected the PCI bus directly to an FPGA but this is the first time we ran an SSN analysis.

The previous design was done with a Virtex-5. We want to port it to an Arria II FPGA

, I know that we ran into some problems with the PCI (in the Virtex-5 FPGA) when connected to some specific backplane PCB, it is possible that this was an SSN problem.

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For the record, you can enter your trace model for all your I/Os and it makes the SSN analyzer more accurate. That's why Altera recommands doing a pre-layout analysis with a 80 or 90% pass-fail criterion and then perform a post-layout analysis with your traces models and your actual PCB stackup with a pass-fail criterion of 50%.

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The SSN analyzer sounds pretty useful then. I'll have to check it out.

Out of interest, how much of your FPGA is the PCI core taking (once you include the backend Avalon-MM interface FIFOs, or whatever you are implementing). When I looked at PCI interfaces a while back, it was cheaper to use a PCI-to-local bus bridge from PLX Technologies. Depending on what FPGA you are using, perhaps a Cyclone GX with x1 PCIe and a PCIe-to-PCI bridge would be cost-effective, and less hassle to design (depending on your PCB real-estate).

eg., PEX8111 x1 PCIe to PCI $23 at Mouser

http://www.mouser.com/productdetail/plx-technology/pex8111-bc66fbcf/?qs=sgaepimzzmtifczob2abwx8plyc9mlqr

Cyclone IV EP4CGX15 $25 at Altera

http://www.buyaltera.com/scripts/partsearch.dll?detail&name=544-1475-nd

Cheers,

Dave

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I would hope they are somewhat related, given that the switching time of an I/O is intimately related to the impedance it is driving :)

If the SSN inside a package is calculated based on di/dt and dv/dt, then without having some form of I/O impedance constraint, do the values Quartus provides give meaningful results?

I haven't used this particular feature of Quartus. If you have some insight into how useful it is, I'd be happy to hear it, and then use the tool on my next board design.

There's so many features to the tools now, its hard to keep up!

Cheers,

Dave

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For the record, you can enter your trace model for all your I/Os and it makes the SSN analyzer more accurate. That's why Altera recommands doing a pre-layout analysis with a 80 or 90% pass-fail criterion and then perform a post-layout analysis with your traces models and your actual PCB stackup with a pass-fail criterion of 50%.

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have you tried to use I/O assignments from Altera's PCI core?

http://www.altera.com/support/kdb/solutions/rd02162009_908.html

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I use the pci compiler from SOPC Builder. It generates a tcl script that generates all PCI constraints except the pins' locations. I then use the fitter to select the proper pins for the PCI to minimize SSN but it can't seem to totally eliminate all SSN errors (i.e. more than 90% SSN) on my 3V pins.

There are mainly 2 reasons :

1 - I have a lot of 3V-I/Os other than the PCI bus itself

2 - The PCI outputs drive a lot of current and it makes SSN worse. I'm not able to control the current-strength using pin planner. I haven't tried using the assignment editor.

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IBIS simulations can show with board routing issues, but i don't think it will help with package related SSN issues

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I would hope they are somewhat related, given that the switching time of an I/O is intimately related to the impedance it is driving :)

If the SSN inside a package is calculated based on di/dt and dv/dt, then without having some form of I/O impedance constraint, do the values Quartus provides give meaningful results?

I haven't used this particular feature of Quartus. If you have some insight into how useful it is, I'd be happy to hear it, and then use the tool on my next board design.

There's so many features to the tools now, its hard to keep up!

Cheers,

Dave

have you tried to use I/O assignments from Altera's PCI core?

http://www.altera.com/support/kdb/solutions/rd02162009_908.html

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Basically, I want to optimize my pinout in order to minimize SSN issues. I have two 3V-banks to drive PCI pins and other GPIOs. No matter what setting I use, even with SSN optimization, the fitter is not able to give me a suitable pinout with regards to SSN.

Basically, I don't assign 3V GPIOs and I let the fitter decide where to place them according to SSN optimization. But I still get SSN errors.

If I manually place some pins (like PCI_AD) and set a "ground" barrier using reserved pins, I can optimize the SSN and I get almost 0 errors for normal GPIOs. However, I'll get SSN errors for the reserved pinds that are connected to ground.

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I haven't used this particular tool within Quartus. It sounds like your second method is the most conservative, and should be safe. Its possible that the SSN errors on the grounded pins are bogus errors; does the documentation indicate what the criteria for an 'error' is?

You can also perform a Hyperlynx (or similar tool) simulation with the driver IBIS models, and the routes extracted from the PCB, and see what the induced voltages are on your traces, i.e., you drive an aggressor trace and see what voltages appear on the victim traces. That'll help determine whether your PCI bus traces are routed too close together.

Cheers,

Dave