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I would hope they are somewhat related, given that the switching time of an I/O is intimately related to the impedance it is driving :)
If the SSN inside a package is calculated based on di/dt and dv/dt, then without having some form of I/O impedance constraint, do the values Quartus provides give meaningful results?
I haven't used this particular feature of Quartus. If you have some insight into how useful it is, I'd be happy to hear it, and then use the tool on my next board design.
There's so many features to the tools now, its hard to keep up!
Cheers,
Dave
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For the record, you can enter your trace model for all your I/Os and it makes the SSN analyzer more accurate. That's why Altera recommands doing a pre-layout analysis with a 80 or 90% pass-fail criterion and then perform a post-layout analysis with your traces models and your actual PCB stackup with a pass-fail criterion of 50%.
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