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Altera_Forum
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14 years ago

SSN and reserve pins as ground

Hi everyone, I started doing SSN analysis on my preliminary designs and I found that I had problems with my standard PCI signals (3.0V) creating SSN on other 3.0V I/Os and vice versa. I tr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Yeah, I'll have to think about it. In all of our previous designs, we connected the PCI bus directly to an FPGA but this is the first time we ran an SSN analysis.

The previous design was done with a Virtex-5. We want to port it to an Arria II FPGA

, I know that we ran into some problems with the PCI (in the Virtex-5 FPGA) when connected to some specific backplane PCB, it is possible that this was an SSN problem.