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Basically, I want to optimize my pinout in order to minimize SSN issues. I have two 3V-banks to drive PCI pins and other GPIOs. No matter what setting I use, even with SSN optimization, the fitter is not able to give me a suitable pinout with regards to SSN.
Basically, I don't assign 3V GPIOs and I let the fitter decide where to place them according to SSN optimization. But I still get SSN errors.
If I manually place some pins (like PCI_AD) and set a "ground" barrier using reserved pins, I can optimize the SSN and I get almost 0 errors for normal GPIOs. However, I'll get SSN errors for the reserved pinds that are connected to ground.
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I haven't used this particular tool within Quartus. It sounds like your second method is the most conservative, and should be safe. Its possible that the SSN errors on the grounded pins are bogus errors; does the documentation indicate what the criteria for an 'error' is?
You can also perform a Hyperlynx (or similar tool) simulation with the driver IBIS models, and the routes extracted from the PCB, and see what the induced voltages are on your traces, i.e., you drive an aggressor trace and see what voltages appear on the victim traces. That'll help determine whether your PCI bus traces are routed too close together.
Cheers,
Dave
Honored Contributor
