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Altera_Forum
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14 years ago

SSN and reserve pins as ground

Hi everyone, I started doing SSN analysis on my preliminary designs and I found that I had problems with my standard PCI signals (3.0V) creating SSN on other 3.0V I/Os and vice versa. I tr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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have you tried to use I/O assignments from Altera's PCI core?

http://www.altera.com/support/kdb/solutions/rd02162009_908.html

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I use the pci compiler from SOPC Builder. It generates a tcl script that generates all PCI constraints except the pins' locations. I then use the fitter to select the proper pins for the PCI to minimize SSN but it can't seem to totally eliminate all SSN errors (i.e. more than 90% SSN) on my 3V pins.

There are mainly 2 reasons :

1 - I have a lot of 3V-I/Os other than the PCI bus itself

2 - The PCI outputs drive a lot of current and it makes SSN worse. I'm not able to control the current-strength using pin planner. I haven't tried using the assignment editor.