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For the record, you can enter your trace model for all your I/Os and it makes the SSN analyzer more accurate. That's why Altera recommands doing a pre-layout analysis with a 80 or 90% pass-fail criterion and then perform a post-layout analysis with your traces models and your actual PCB stackup with a pass-fail criterion of 50%.
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The SSN analyzer sounds pretty useful then. I'll have to check it out.
Out of interest, how much of your FPGA is the PCI core taking (once you include the backend Avalon-MM interface FIFOs, or whatever you are implementing). When I looked at PCI interfaces a while back, it was cheaper to use a PCI-to-local bus bridge from PLX Technologies. Depending on what FPGA you are using, perhaps a Cyclone GX with x1 PCIe and a PCIe-to-PCI bridge would be cost-effective, and less hassle to design (depending on your PCB real-estate).
eg., PEX8111 x1 PCIe to PCI $23 at Mouser
http://www.mouser.com/productdetail/plx-technology/pex8111-bc66fbcf/?qs=sgaepimzzmtifczob2abwx8plyc9mlqr Cyclone IV EP4CGX15 $25 at Altera
http://www.buyaltera.com/scripts/partsearch.dll?detail&name=544-1475-nd Cheers,
Dave
Honored Contributor
