SSN and reserve pins as ground

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I mean SSN errors. i.e. more than 80 or 90% of noise on the reserved ground pins (I set them using pin planner)

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Reserving pins as ground in the pin planner does nothing but tell the pin planner you have connected those pins to ground. If you haven't actually done that on the PCB, then you will not gain any advantage.

Cheers,

Dave

Hi,

The PCB isn't done yet, I'm trying to perform pre-layout SSN optimisation as suggested in " the "Design Guidelines for Arria II Device" application note

Basically, I want to optimize my pinout in order to minimize SSN issues. I have two 3V-banks to drive PCI pins and other GPIOs. No matter what setting I use, even with SSN optimization, the fitter is not able to give me a suitable pinout with regards to SSN.

Basically, I don't assign 3V GPIOs and I let the fitter decide where to place them according to SSN optimization. But I still get SSN errors.

If I manually place some pins (like PCI_AD) and set a "ground" barrier using reserved pins, I can optimize the SSN and I get almost 0 errors for normal GPIOs. However, I'll get SSN errors for the reserved pinds that are connected to ground.

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Basically, I want to optimize my pinout in order to minimize SSN issues. I have two 3V-banks to drive PCI pins and other GPIOs. No matter what setting I use, even with SSN optimization, the fitter is not able to give me a suitable pinout with regards to SSN.

Basically, I don't assign 3V GPIOs and I let the fitter decide where to place them according to SSN optimization. But I still get SSN errors.

If I manually place some pins (like PCI_AD) and set a "ground" barrier using reserved pins, I can optimize the SSN and I get almost 0 errors for normal GPIOs. However, I'll get SSN errors for the reserved pinds that are connected to ground.

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I haven't used this particular tool within Quartus. It sounds like your second method is the most conservative, and should be safe. Its possible that the SSN errors on the grounded pins are bogus errors; does the documentation indicate what the criteria for an 'error' is?

You can also perform a Hyperlynx (or similar tool) simulation with the driver IBIS models, and the routes extracted from the PCB, and see what the induced voltages are on your traces, i.e., you drive an aggressor trace and see what voltages appear on the victim traces. That'll help determine whether your PCI bus traces are routed too close together.

Cheers,

Dave

have you tried to use I/O assignments from Altera's PCI core?

http://www.altera.com/support/kdb/solutions/rd02162009_908.html

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IBIS simulations can show with board routing issues, but i don't think it will help with package related SSN issues

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I would hope they are somewhat related, given that the switching time of an I/O is intimately related to the impedance it is driving :)

If the SSN inside a package is calculated based on di/dt and dv/dt, then without having some form of I/O impedance constraint, do the values Quartus provides give meaningful results?

I haven't used this particular feature of Quartus. If you have some insight into how useful it is, I'd be happy to hear it, and then use the tool on my next board design.

There's so many features to the tools now, its hard to keep up!

Cheers,

Dave

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have you tried to use I/O assignments from Altera's PCI core?

http://www.altera.com/support/kdb/solutions/rd02162009_908.html

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I use the pci compiler from SOPC Builder. It generates a tcl script that generates all PCI constraints except the pins' locations. I then use the fitter to select the proper pins for the PCI to minimize SSN but it can't seem to totally eliminate all SSN errors (i.e. more than 90% SSN) on my 3V pins.

There are mainly 2 reasons :

1 - I have a lot of 3V-I/Os other than the PCI bus itself

2 - The PCI outputs drive a lot of current and it makes SSN worse. I'm not able to control the current-strength using pin planner. I haven't tried using the assignment editor.