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Honored Contributor
Honored Contributorskew poblem!
Hi,
I am writing vhdl code of a simple microprocessor.. The simulation in modelsim works good, but when I compiled the design in Quartus, I got many warning msgs, the last one says that the circuit may not works because of skew problems. And it actually didn't work on the altera DE2 card. Is there any one than can help me to get around this "clock skew" problem? With regards4 Replies
Altera_ForumThank you very much kaz
Your last note helped me to solve all the problems. I included the clock process with the state process. The design has become really sychronised now. With regards- Altera_Forum
To answer your question you need to look at the source of clk, not its destination process. Moreover, I have some doubt about your design being synchronised enough on the clk since only one process is clked.
- Altera_Forum
Thank you KAZ for your answer
The only process that I use clock in it, is the following process: reset_p: process(reset,clk,nextstate) begin if reset = '1' then currentstate <= S0; elsif rising_edge(clk) then currentstate <= nextstate; end if; end process; I have then another process that deals with currentstate Can this situation cosidered as a gated clock? - Altera_Forum
The issue of clk skew has been raised in many posts.
It is mostly due to gating of clk. A clean non-gated clk dosn't end up in skew(quartus and silicon look after that and clk delay is not allowed to exceed data delay at any register, unless unknowingly the designer gates the clk signal). If you have to gate the clk then there are some conditions; clk should be made global and should be registered at exit point(on another clk).
