skew poblem!

The issue of clk skew has been raised in many posts.

It is mostly due to gating of clk. A clean non-gated clk dosn't end up in skew(quartus and silicon look after that and clk delay is not allowed to exceed data delay at any register, unless unknowingly the designer gates the clk signal). If you have to gate the clk then there are some conditions; clk should be made global and should be registered at exit point(on another clk).