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Honored Contributor
Honored Contributorskew poblem!
Hi, I am writing vhdl code of a simple microprocessor.. The simulation in modelsim works good, but when I compiled the design in Quartus, I got many warning msgs, the last one says that the ci...
Altera_ForumHonored Contributor
Honored ContributorTo answer your question you need to look at the source of clk, not its destination process. Moreover, I have some doubt about your design being synchronised enough on the clk since only one process is clked.
