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Altera_Forum's avatar
Altera_Forum
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17 years ago

skew poblem!

Hi, I am writing vhdl code of a simple microprocessor.. The simulation in modelsim works good, but when I compiled the design in Quartus, I got many warning msgs, the last one says that the ci...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thank you very much kaz

Your last note helped me to solve all the problems.

I included the clock process with the state process.

The design has become really sychronised now.

With regards