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Honored Contributor
Honored Contributorskew poblem!
Hi, I am writing vhdl code of a simple microprocessor.. The simulation in modelsim works good, but when I compiled the design in Quartus, I got many warning msgs, the last one says that the ci...
Altera_ForumHonored Contributor
Honored ContributorThank you KAZ for your answer
The only process that I use clock in it, is the following process: reset_p: process(reset,clk,nextstate) begin if reset = '1' then currentstate <= S0; elsif rising_edge(clk) then currentstate <= nextstate; end if; end process; I have then another process that deals with currentstate Can this situation cosidered as a gated clock?
