Forum Discussion
Honored Contributorsimple verilog to vhdl translation question
hello,
in a verilog module i found a declaration, that is, output reg ack; in vhdl translation, i can simply write : signal ack; am i right??12 Replies
Altera_ForumMy mistake
You also need use ieee.numeric_std.all; http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf Has some really good info on this kind of stuff- Altera_Forum
4 downto 0 must not be changed. i did what you tell but i got error:
to_integer is used but not declared. i already added use ieee.std_logic_unsigned.all - Altera_Forum
I think it should be (3 downto 0) to be an integer
- Altera_Forum
Array indexes have to be an integer
so for internal_reg(addr(4 downto 2)) <= dati; --line 70 you need to cast addr(4 downto 2) into an integer something like include the library use ieee.std_logic_unsigned.all internal_reg(to_integer( unsigned(addr(4 downto 2)))) <= dat; you need to cast a std_logic_vector to an unsigned, then an unsigned to an integer. - Altera_Forum
i cannot do that because dati is 32 bits width. I have an idea which is, i must convert the addr(4 downto 0) to integer.in that means internal_regs(integer) which corresponds one of the array of 32 bits. but to convert this (4 downto 2) into integer is another problem. i have tried conv_integer(addr(4 downto 0)) but failed
- Altera_Forum
It seems that you are trying to write three bytes
internal_reg(addr(4 downto 2)) into a 32-bit register, so you should adjust the indexes in order to write 4 bytes instead of 3. - Altera_Forum
nope..sorry..internal_regs what i wrote my vhdl programme..with 's'
- Altera_Forum
Is it because you wrote "internal_reg" instead of "internal_regs"?
- Altera_Forum
thx. really help me. i added to your reputation. Another question:
Verilog codes: reg [31:0] internal_regs[3:0]; input [31 downto 0] dati; always@(posedge clk) begin .. internal regs[addr[4:2]] <=dati; .. end I have write my vhdl code for the line 70 as: internal_reg(addr(4 downto 2)) <= dati; --line 70 but i got the following error: Error (10381): VHDL Type Mismatch error at wb_prom.vhd(70): indexed name returns a value whose type does not match "integer", the type of the target expression how to change the code in line 70?? - Altera_Forum
reg [31:0] internal_regs[3:0]
This is a 2 dimensional array i.e. an array of 16 * 32 bit values You will need to define a type like type regs_type is array (0 to 15) of std_logic_vector(31 downto 0) then a signal signal internal_regs : regs_type; elements are references as internal_regs(0) <= X"12345678"; or for bit access internal_regs(0, 1) <= '0'; etc Hope this helps
