simple verilog to vhdl translation question

thx. really help me. i added to your reputation. Another question:

Verilog codes:

reg [31:0] internal_regs[3:0];

input [31 downto 0] dati;

always@(posedge clk)

begin

..

internal regs[addr[4:2]] <=dati;

..

end

I have write my vhdl code for the line 70 as:

internal_reg(addr(4 downto 2)) <= dati; --line 70

but i got the following error:

Error (10381): VHDL Type Mismatch error at wb_prom.vhd(70): indexed name returns a value whose type does not match "integer", the type of the target expression

how to change the code in line 70??