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Altera_Forum
Honored Contributor
Honored Contributorsimple verilog to vhdl translation question
hello, in a verilog module i found a declaration, that is, output reg ack; in vhdl translation, i can simply write : signal ack; am i right??
Altera_ForumHonored Contributor
Honored Contributor4 downto 0 must not be changed. i did what you tell but i got error:
to_integer is used but not declared. i already added use ieee.std_logic_unsigned.all
