simple verilog to vhdl translation question

reg [31:0] internal_regs[3:0]

This is a 2 dimensional array i.e. an array of 16 * 32 bit values

You will need to define a type like

type regs_type is array (0 to 15) of std_logic_vector(31 downto 0)

then a signal

signal internal_regs : regs_type;

elements are references as

internal_regs(0) <= X"12345678";

or for bit access

internal_regs(0, 1) <= '0';

etc

Hope this helps