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Altera_Forum
Honored Contributor
Honored Contributorsimple verilog to vhdl translation question
hello, in a verilog module i found a declaration, that is, output reg ack; in vhdl translation, i can simply write : signal ack; am i right??
Altera_ForumHonored Contributor
Honored ContributorArray indexes have to be an integer
so for internal_reg(addr(4 downto 2)) <= dati; --line 70 you need to cast addr(4 downto 2) into an integer something like include the library use ieee.std_logic_unsigned.all internal_reg(to_integer( unsigned(addr(4 downto 2)))) <= dat; you need to cast a std_logic_vector to an unsigned, then an unsigned to an integer.
