Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorsimple verilog to vhdl translation question
hello, in a verilog module i found a declaration, that is, output reg ack; in vhdl translation, i can simply write : signal ack; am i right??
Altera_ForumHonored Contributor
Honored ContributorIt seems that you are trying to write three bytes
internal_reg(addr(4 downto 2)) into a 32-bit register, so you should adjust the indexes in order to write 4 bytes instead of 3.
