simple verilog to vhdl translation question

i cannot do that because dati is 32 bits width. I have an idea which is, i must convert the addr(4 downto 0) to integer.in that means internal_regs(integer) which corresponds one of the array of 32 bits. but to convert this (4 downto 2) into integer is another problem. i have tried conv_integer(addr(4 downto 0)) but failed