Signal Tap Logic Analyzer Interferes with Normal Operation in MAX10 FPGA

Question

Hi,I am facing a problem when I enable Signal Tap Logic Analyzer to monitor I/Os. I have a relatively big project (with tens of modules) and it operates normally when there is no Signal Tap Logic Analyzer. But when I enable the feature to monitor the I/Os, I've identified a malfunction in one module responsible for LPC-to-UART conversion. I cannot confirm the proper functioning of other modules as I am unable to monitor them. The malfunction in the specified module is evident through unsuccessful UART read/write operations.Could Signal Tap Logic Analyzer potentially interfere with the FPGA's normal operation?Note 1: I am utilizing the main 24MHz input clock as the sampling rate in Signal Tap Logic Analyzer. This clock is also employed in all modules. The Signal Tap RAM type is set to Auto, and the sample depth is 64.Note 2: When I reduce the number of signals to monitor in Signal Tap, the UART reading operation starts to function correctly. However, writing operations remain problematic. This suggests that the level of interference changes based on the number of monitored signals.Thanks,Reza,

fvm · Answer

Hi,this usually happens if the design has timing problems, either explicite (failing timing constraints) or hidden (not correctly synchronizing external signals or signals crossing clock domains).Adding signal tap changes routing of the complete design and can therefore reveal hidden problems.Does the design without and with signal tap pass timing analysis? An UART usually involves external signals, e.g. RxD. Are they synchronized correctly before entering your logic?

reza5 · Answer

Hi,Timing Analyzer shows some violation in UART section. This might be the problem.As I am new to Intel FPGA, could you please clarify what is meant by "synchronized correctly before entering your logic"?Thanks,

fvm · Answer

Hi, processing RxD is a good example for need of
synchronization. Falling edge of start bit will usually affect more than one register bit. If the edge occurs near to active UART clock edge, there's a good change that some registers see start bit at one clock and others at the next, causing unexpected and possibly even unrecoverable states. You don't need metastability to achieve this, just normal clock and signal delay skew. The solution is to synchronize all foreign signals like RxD with a 2 or 3 register chain. One register is good to get rid of 99.9 % of failures, the others are needed to fight metastability.

shengn_altera · Answer

Hi,May be you can try to increase the pipeline factor in the Signal Configuration pane of Signal-Tap to boost the fMAX check this link https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/specifying-pipeline-settings.htmlThanks,Best Regards,Sheng

shengn_altera · Answer

Hi,Do you have any further concern or consideration?Thanks,Best Regards,Sheng

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Signal Tap Logic Analyzer Interferes with Normal Operation in MAX10 FPGA

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