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Reza5's avatar
Reza5
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2 years ago

Signal Tap Logic Analyzer Interferes with Normal Operation in MAX10 FPGA

Hi, I am facing a problem when I enable Signal Tap Logic Analyzer to monitor I/Os. I have a relatively big project (with tens of modules) and it operates normally when there is no Signal Tap Logic A...
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Generic Io
Programmable Logic Device
Reza5's avatar
Reza5
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2 years ago

Hi,

Timing Analyzer shows some violation in UART section. This might be the problem.

As I am new to Intel FPGA, could you please clarify what is meant by "synchronized correctly before entering your logic"?

Thanks,

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago
    Hi, processing RxD is a good example for need of
    synchronization. Falling edge of start bit will usually affect more than one register bit. If the edge occurs near to active UART clock edge, there's a good change that some registers see start bit at one clock and others at the next, causing unexpected and possibly even unrecoverable states. You don't need metastability to achieve this, just normal clock and signal delay skew. The solution is to synchronize all foreign signals like RxD with a 2 or 3 register chain. One register is good to get rid of 99.9 % of failures, the others are needed to fight metastability.