Signal Tap Logic Analyzer Interferes with Normal Operation in MAX10 FPGA

Hi,
this usually happens if the design has timing problems, either explicite (failing timing constraints) or hidden (not correctly synchronizing external signals or signals crossing clock domains).

Adding signal tap changes routing of the complete design and can therefore reveal hidden problems.

Does the design without and with signal tap pass timing analysis? An UART usually involves external signals, e.g. RxD. Are they synchronized correctly before entering your logic?