Forum Discussion
Reza5
New Contributor
New ContributorSignal Tap Logic Analyzer Interferes with Normal Operation in MAX10 FPGA
Hi, I am facing a problem when I enable Signal Tap Logic Analyzer to monitor I/Os. I have a relatively big project (with tens of modules) and it operates normally when there is no Signal Tap Logic A...
FvM
Super Contributor
Super ContributorHi,
this usually happens if the design has timing problems, either explicite (failing timing constraints) or hidden (not correctly synchronizing external signals or signals crossing clock domains).
Adding signal tap changes routing of the complete design and can therefore reveal hidden problems.
Does the design without and with signal tap pass timing analysis? An UART usually involves external signals, e.g. RxD. Are they synchronized correctly before entering your logic?
this usually happens if the design has timing problems, either explicite (failing timing constraints) or hidden (not correctly synchronizing external signals or signals crossing clock domains).
Adding signal tap changes routing of the complete design and can therefore reveal hidden problems.
Does the design without and with signal tap pass timing analysis? An UART usually involves external signals, e.g. RxD. Are they synchronized correctly before entering your logic?
