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Reza5
New Contributor
New ContributorSignal Tap Logic Analyzer Interferes with Normal Operation in MAX10 FPGA
Hi, I am facing a problem when I enable Signal Tap Logic Analyzer to monitor I/Os. I have a relatively big project (with tens of modules) and it operates normally when there is no Signal Tap Logic A...
ShengN_altera
Super Contributor
Super ContributorHi,
May be you can try to increase the pipeline factor in the Signal Configuration pane of Signal-Tap to boost the fMAX check this link https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/specifying-pipeline-settings.html
Thanks,
Best Regards,
Sheng
