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Reza5's avatar
Reza5
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2 years ago

Signal Tap Logic Analyzer Interferes with Normal Operation in MAX10 FPGA

Hi, I am facing a problem when I enable Signal Tap Logic Analyzer to monitor I/Os. I have a relatively big project (with tens of modules) and it operates normally when there is no Signal Tap Logic A...
Configuration
Generic Io
Programmable Logic Device
ShengN_altera's avatar
ShengN_altera
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2 years ago

Hi,


Do you have any further concern or consideration?


Thanks,

Best Regards,

Sheng


Reza5's avatar
Reza5
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2 years ago

Hi Sheng,

Not at the moment, I need to address a timing issue in my project to see if I can resolve the problem. Thank you for your assistance.

Also, thanks to FvM for his time

Thanks,

Best Regards,

Reza,