Shift Register triggers occassionally on both clock edges

Question

Good morning community, in my project a MAX10 M08 FPGA serves as an interface between a microcontroller and an ADC board with 32 channels. In order to parallelize the serial data from the board I developed a shift register. This register shall only read the first 512 bits of a data stream. Therefore a counter is included.-- serial-parallel converter synchronous to falling edge of DCLKp_ser_par_dclk : process (DCLK,nRES) isbegin&nbsp; &nbsp;if (nRES = '0') then&nbsp; &nbsp; &nbsp;dout0_shr_dclk &lt;= (others =&gt; '0');&nbsp; &nbsp; &nbsp;dout1_shr_dclk &lt;= (others =&gt; '0');&nbsp; &nbsp; &nbsp;mod1023_count_i &lt;= 0;&nbsp; elsif (falling_edge(DCLK)) then&nbsp; &nbsp; -- resets counter when nDRDY active&nbsp; &nbsp; if (nDRDY = '1') then&nbsp;&nbsp; &nbsp; &nbsp; mod1023_count_i &lt;= 0;&nbsp;&nbsp; &nbsp; elsif (mod1023_count_i &lt; 512) then&nbsp; &nbsp; &nbsp; mod1023_count_i &lt;= mod1023_count_i + 1;&nbsp; &nbsp; end if;&nbsp; &nbsp; -- counter masks the 512 DCLK clock edges without data&nbsp; &nbsp; if (mod1023_count_i &lt; 512) then&nbsp; &nbsp; &nbsp; -- shift-registers, alert bit, address bits, CRC bits shifted, maybe later omitted&nbsp; &nbsp; &nbsp; dout0_shr_dclk(0) &lt;= DOUT0;&nbsp; &nbsp; &nbsp; dout1_shr_dclk(0) &lt;= DOUT1;&nbsp; &nbsp; &nbsp; dout0_shr_dclk((snr_length - 1) downto 1) &lt;= dout0_shr_dclk((snr_length - 2) downto 0);&nbsp; &nbsp; &nbsp; dout1_shr_dclk((snr_length - 1) downto 1) &lt;= dout1_shr_dclk((snr_length - 2) downto 0);&nbsp; &nbsp; -- no shifting&nbsp; &nbsp; else&nbsp; &nbsp; &nbsp; dout1_shr_dclk &lt;= dout1_shr_dclk;&nbsp; &nbsp; &nbsp; dout0_shr_dclk &lt;= dout0_shr_dclk;&nbsp; &nbsp; end if;&nbsp;end if;end process p_ser_par_dclk;&nbsp;The data from the AD converters contains the channel number. Therefore there must be regular data patterns in the 512 bit wide vector when a complete set of 16*32bit have been written into the FIFO. I could never see this pattern when I visualized the internal data with the signal tap analyzer. What I can occassionally see is that the shift registers and the counter triggers at the wrong edge. This is a severe error. What could be the reason?Best regardsChristof Abt&nbsp;&nbsp;

fvm · Answer

Hi Christof,a possible reason is ringing external clock. Signaltap recording isn't very informative, it's not clear how dclk is related to acquisition clock.Regars Frank

sstrell · Answer

Signal names on the Signal Tap capture would be helpful. Is your design meeting timing?

The code could also use some clean up, combining the if blocks for the counter operation and performing the shift.

And as mentioned, what are you using as the acquisition clock in Signal Tap?

christofabt · Answer

Good morning, thank you for your reply. Sorry, I should have included the signal names. The counter and the shift operation could be combined but the original code should not cause any problems. Everything is synchronous to the falling edge of DCLK. The acquisition clock is very low, around 2MHz.

sstrell · Answer

2 MHz?&nbsp; Why are you using that?&nbsp; What is the frequency of dclk?&nbsp; That should be your acquisition clock in Signal Tap.&nbsp; A faster clock provides much better sampling.

christofabt · Answer

The data rate is 2Mbs. I use the falling edge of DCLK to sample DOUT0 and DOUT1

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Shift Register triggers occassionally on both clock edges

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