New Contributor
Super ContributorSignal names on the Signal Tap capture would be helpful. Is your design meeting timing?
The code could also use some clean up, combining the if blocks for the counter operation and performing the shift.
And as mentioned, what are you using as the acquisition clock in Signal Tap?
New ContributorGood morning, thank you for your reply. Sorry, I should have included the signal names. The counter and the shift operation could be combined but the original code should not cause any problems. Everything is synchronous to the falling edge of DCLK. The acquisition clock is very low, around 2MHz.
Super Contributor2 MHz? Why are you using that? What is the frequency of dclk? That should be your acquisition clock in Signal Tap. A faster clock provides much better sampling.
New ContributorThe data rate is 2Mbs. I use the falling edge of DCLK to sample DOUT0 and DOUT1
