Quartus Pro simulation libraries for Riviera Pro
Hello, Using Quartus Pro 25.1, when trying to use the simulation library compiler tool to generate simulation libraries for Riviera Pro, the following error appears: Error: # ACOM: Error: COMP96_0001: Cannot find source file "c:/altera_pro/25.1/quartus/eda/sim_lib/altera_syn_attributes.vhd". Checking the folder content, it seems there are several missing files. This scenario has been reproduced in several machines. Could you please help us to solve this?
Agilex5 A5EB013BB23BE4S BSDL
Hello, I need a bsdl file for this FPGA device, but it is not available on the Agilex-5 BSDL files page: https://www.intel.com/content/www/us/en/support/programmable/support-resources/board-layout/agilex-bsdl.html?f:guidetm9B04DD8D7CC445359916A9509D5E6911=%5BIntel%20Agilex%C2%AE%205%20FPGAs%20and%20SoC%20FPGAs%5D Can you please share it with me? Best regards, Igor
Backplane Ethernet 10GBASE-KR PHY FPGA IP
I would like to know more information about the Intel\Altera Backplane Ethernet 10GBASE-KR PHY FPGA IP . Can it be implemented in the Agilex 5 FPGA ? If not are there any plans to incorporate it there and what would be the time frame ? Also what type of license is offered. I tried the site contact :- https://www.altera.com/products/ip/po-3078/backplane-ethernet-10gbase-kr-phy-fpga-ip twice but I got no response ???
System PLL of Agliex5 PCIE example design cannot be locked after configuration
Hi all, The device is Agilex 5 E series FPGA, development kit is plugged in main board via a x16 card edge. Both System PLL reference clock and PCIE AXI Stream Hard IP reference clock are driven from PCIE card edge. After power up, IO PLL locked but System PLL cannot be locked, PCIE hard IP remains in reset status, regardless the configuration method of FPGA (that is, via JTAG or QSPI flash). Here are my questions: 1、Is it valid for System PLL to have its reference clock driven from PCIE card edge？According to 4.1.1 of GTS AXI Streaming IP for PCI Express* User Guide: Agilex 5 and Agilex 3 FPGAs and SoCs (ug813754), reference clock for System PLL should from a independent and free-running local clock source. 2、If the answer of above question is positve, how should I debug to make the System PLL work? Best regards.
Avalon-ST configuration with Agilex 3 fails
Hi, I have implemented a kind of passive serial programming from a CPU using SPI and a shift register. The signals nSTATUS, nCONFIG, CONF_DONE, READY, and VALID are directly controlled by GPIOs. This works well except after a power cycle. After the system has powered up, the programming fails — CONF_DONE does not go high. All retries afterward succeed. I already went through the debugging guidelines but couldn’t find an issue. However, I have observed two things: The nSTATUS pin follows exactly the timing of the nCONFIG pin during the first attempt. Normally, nSTATUS is delayed and goes high later. The CPU must finish the complete programming cycle before retrying; otherwise, the FPGA remains stuck in this erroneous state. I recorded some curves with a logic analyzer: full_timing.png: Power cycle First configuration cycle fails Retry works Another cycle also works 2_start.png: Beginning of cycle 2. Here, the nSTATUS pin follows exactly the timing of the nCONFIG pin. 2_3_restart.png: End of cycle 2 and beginning of cycle 3. 4_start.png: Another configuration cycle that works. Any idea what could cause this problem? Regards Samuel
Agilex 7I-Series Device Errata and User Guide: Why my answers are deleted all the time:
Am asking to help with obtaining [ Agilex™ 7 F-Series and I-Series ES Device Errata and User Guidelines] datasheets. But all my answers with sreenshots of other Altera/Intel documents regarding this datasheet link and document number are always deleted. Why deleted ? Terrible support ! Wasted $15K on DK-SI-AGI040FES Kit, cannot get access to errata document, got help request questions deleted from Alterra board This what was in Intel/Altera original datasheet: For Information about the Agilex & Device Errata Sheet and User Guidelines [ES-1069] and Agilex 7 Known Issues List, contact Intel Premier Support and quote ID #15011992053. Now in Altera datasheet (Agilex 7 Known Issues List) its mentioned as Agilex 7 F-Series and I-Series Device Errata and User Guide [Agilex 7 Known Issues List] PDF is public open while [Agilex 7 F-Series and I-Series Device Errata and User Guide] is NOT Need help obtaining Agilex 7 I errata !
Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
Does the 1SG280LU2F50E2VG support bitfile encryption
I am attempting to encrypt and load an image to the 1SG280LU2F50E2VG on our Stratix 10 GX development kit following the instructions in AN 970: Intel® Stratix® 10 Security Tutorial. When I attempt to download the "root.qky" to the FPGA I see: Info(209060): Started Programmer operation at Thu Feb 12 18:01:59 2026 Info(18942): Configuring device index 1 Info(18943): Configuration succeeded at device index 1 Info(20091): Programming public key on device 1 Error(209012): Operation failed Info(209061): Ended Programmer operation at Thu Feb 12 18:02:02 2026 Is the FPGA on the development kit compatible with encryption?
