Forum Discussion

ChristofAbt's avatar
ChristofAbt
Icon for New Contributor rankNew Contributor
5 days ago

Shift Register triggers occassionally on both clock edges

Good morning community, in my project a MAX10 M08 FPGA serves as an interface between a microcontroller and an ADC board with 32 channels. In order to parallelize the serial data from the board I dev...
Core Logic
Programmable Logic Device
quality|reliability
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 days ago

There are a few things you can try:
1) Set DCLK as global clock 

2) Constrain the source‑synchronous input properly in your sdc e.g. set_input_delay

3) Synchronize async signals into the DCLK domain:
 - Two-stage synchronizer for nDRDY and any other async control; sample DOUT* only with respect to the synchronized signals.