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ChristofAbt's avatar
ChristofAbt
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5 days ago

Shift Register triggers occassionally on both clock edges

Good morning community, in my project a MAX10 M08 FPGA serves as an interface between a microcontroller and an ADC board with 32 channels. In order to parallelize the serial data from the board I dev...
Core Logic
Programmable Logic Device
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ChristofAbt's avatar
ChristofAbt
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4 days ago

Good morning, thank you for your reply. Sorry, I should have included the signal names. The counter and the shift operation could be combined but the original code should not cause any problems. Everything is synchronous to the falling edge of DCLK. The acquisition clock is very low, around 2MHz.

sstrell's avatar
sstrell
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4 days ago

2 MHz?  Why are you using that?  What is the frequency of dclk?  That should be your acquisition clock in Signal Tap.  A faster clock provides much better sampling.

  • ChristofAbt's avatar
    ChristofAbt
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    3 days ago

    The data rate is 2Mbs. I use the falling edge of DCLK to sample DOUT0 and DOUT1