Altera_Forum
Honored Contributor
Honored Contributorscfifo-what is the problem
from this vhdl code,i make this as an avalon slave component on the cyclon2 device, and i get the output (sender) as peaks (nearly impulse) , what may be the problem?
is it something related to lpm_showahead or use_eab values,or rdrequest and wrrequest timing? library altera;use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.all;
library lpm;
use lpm.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tele is
port (
-- inputs:
signal address : in std_logic_vector (1 downto 0);
signal chipselect : in std_logic;
signal clk : in std_logic;
signal reset_n : in std_logic;
signal write_n : in std_logic;
signal writedata : in std_logic_vector (7 downto 0);
-- outputs:
--signal the_output : out std_logic;
signal tx_empty : out std_logic;
signal tx_full : out std_logic;
signal tx_used : out std_logic_vector (5 downto 0);
signal sender : out std_logic_vector (7 downto 0)
);
end entity tele;
architecture europa of tele is
component scfifo is
generic (
lpm_numwords : integer;
lpm_showahead : string;
lpm_width : integer;
lpm_widthu : integer;
overflow_checking : string;
underflow_checking : string;
use_eab : string
);
port (
signal full : out std_logic;
signal usedw : out std_logic_vector (5 downto 0);
signal q : out std_logic_vector (7 downto 0);
signal empty : out std_logic;
signal rdreq : in std_logic;
signal data : in std_logic_vector (7 downto 0);
signal sclr : in std_logic;
signal clock : in std_logic;
signal wrreq : in std_logic
);
end component scfifo;
signal wrrequest : std_logic;
signal rdrequest : std_logic;
signal sclr_me : std_logic;
begin
write_fifo : scfifo
generic map(
lpm_numwords => 64,
lpm_showahead => "off",
lpm_width => 8,
lpm_widthu => 6,
overflow_checking => "on",
underflow_checking => "on",
use_eab => "off"
)
port map(
clock => clk,
data => writedata,
empty => tx_empty,
full => tx_full,
q => sender,
rdreq => rdrequest,
sclr => sclr_me,
usedw => tx_used,
wrreq => wrrequest
);
rdrequest <='1';
sclr_me <= '0';
wrrequest <= '1';
end europa;
